1. Field of the Invention
This invention relates in general to characterizing cooling devices and cooling packages for electronic components and more particularly, to an apparatus and method of thermal characterization of a cooling device under non-uniform heat loads.
2. Description of the Related Art
Microprocessor performance has improved significantly over the last decade. To effect this improvement in device performance, the density of circuitry has increased. More and more transistors are fabricated in smaller chip size. This has in turn, led to an exponential rise in package power densities, and this trend is expected to continue into the foreseeable future. Almost all the electrical energy consumed by the chip package is released into the surroundings as heat, which thus places an enormous burden on the cooling device and cooling package.
Existing cooling technologies typically utilize air or water to carry the heat away from the chip. Heat sinks with heat pipes or vapor chambers are commonly used air-cooling devices, while cold-plates, of mini and micro scales, are most predominant in water-cooling. These devices are attached to the silicon chip via a thermal interface. In many cooling packages, three components can be distinguished: i) the cooling device; ii) the thermal conductive interface between the cooling device and the chip; and iii) the chip or semiconductor device itself. Each of these is described further below. In the following, for discussion purposes, the cooling device is referred to as the heat sink which may comprise a fan, copper fins, a cold plate, mini-channels, mini-ducts, micro-channels, micro-ducts, and other similar structures. The cooling package includes the cooling device, the electronic device such as a semiconductor chip, and a thermal interface material between the chip and the cooling device.
FIGS. 1 and 2 show prior art air-cooled and liquid-cooled chip, respectively. Referring to FIG. 1, an air-cooled fin-type heat sink 102 is coupled to a silicon chip 104. The heat sink 102 includes a plurality of cooling fins 106 that are made of a highly thermally conducting material such as copper or aluminum. The fin structure maximizes surface area and extracts the heat away from the chip, and transfers the heat to an ambient environment 108. The heat sink 102 can also includes an internal heat pipe 110 having a wick structure and located between the cooling fins 106 and the chip 104 and a thermally conductive plate 112 located between the heat pipe 110 and the chip 104. Finally, a thermally conductive interface 114, such as grease, epoxy, or solder, couples the heat sink 102 to the chip 104 and allows heat to transfer from the chip 104 to the heat sink 102. For reference purposes, the whole structure 100 is referred to as the cooling “package.”
Referring now to FIG. 2, a liquid-cooled heat sink 202 is shown coupled to a silicon chip 104. The liquid-cooled heat sink 202 is a sealed environment that does not necessarily rely on the environment for heat dissipation, but instead provides a path for the circulation of liquid. The liquid is able to carry away a portion of the heat to a chiller or some other heat extractor (which could be the environment). The liquid cooled heat sink 202 is coupled to the chip 104 by a thermally conductive interface 114. Similar to that shown in FIG. 1, the cold plate 202 of FIG. 2 is the actual cooling device while the whole structure 200 is referred to as the cooling package. Cooling package 200 includes the interface 114 and the chip 104. It should be noted that the cold plate 202 comprises mini-channels, micro-channels, mini-ducts and micro-ducts and other forms of macro/mini/micro coldplates.
In addition to a general rise in the power dissipation due to the above-mentioned increase in transistor density, microprocessors and other circuitry have been optimized for performance, which has resulted in high heat zones or areas on the device. These zones display much higher power densities and lead to ‘hot spots’ on the chip. FIG. 3 is a prior art chip power map showing power distribution. FIG. 4 depicts a prior art temperature distribution on the surface of the cooling device, resulting from the power map of FIG. 3 when the device 104 is cooled as discussed with reference to prior art structures. The spatial non-uniformity of the chip's power distribution causes a corresponding non-uniformity in power and temperature on the surface of the cooling device that is in contact with the chip by means of the thermally conductive interface 114. This phenomenon can adversely affect the thermal performance of the cooling device, which is typically designed to function and tested under a more spatially uniform heat load.
Heat pipes 110 or vapor chambers have an evaporator section (not shown) that uses known liquid phase change via evaporation or boiling of the resident liquid. This enables the extraction of large amounts of heat from the chip surface. Both evaporation and boiling rates, are significantly influenced by the magnitude of heat flux and heat flux distribution over the surface in contact with the liquid undergoing phase change. Specifically, degradation in cooling ability of the heat pipe 110 occurs at areas of high power density within the device. Thus, when employing a heat pipe or a vapor chamber to cool a microprocessor or an electronic device, if there is a large non-uniformity in the power density of the chip, the boiling and/or evaporation in the evaporator region over the chip and interface will also be non-uniform. The resultant cooling heat transfer coefficient is a dependent function on the local heat flux distribution on the evaporator surface.
To illustrate this principle, FIG. 5 shows a prior art fully-operational silicon chip 104. The chip 104 has three distinct power density areas: a low power density area 502; a moderate power density area 504; and a high power density 506. Located directly above and coupled to the chip 104 is a heat pipe 110 containing a liquid 508. Within the heat pipe 110 and directly above the moderate power density area 504 of the chip 104, is an area 514 where the liquid 508 is boiling. At this point, the phase change is rapidly occurring and the cooling effect of the heat pipe 110 is at a maximum. At area 512, directly above the low power density area 502 of the operating chip 104, is an area of little phase change in the cooling liquid 508 (most commonly water), and, therefore, reduced cooling of the chip 104. Finally, at area 516, directly above the high power density area 506 of the chip 104, an excess amount of vapor generation is occurring in the liquid 508. The excess amount of vapor generation creates a blanket of vapor 518 that prevents the liquid 508 from contacting the plate 112 and efficiently dissipating the heat from the plate 112, thereby causing the cooling coefficient of the cooling device 110 to drop off rapidly.
FIG. 6 a prior art graphic illustrates how the variation of a boiling or evaporation cooling coefficient is a function of input power density. Three points along the graph 612, 614, and 616, correspond to the same areas, 512, 514, and 516, in FIG. 5. In FIG. 6, it can be seen that the cooling coefficient increases with power density until it reaches an optimal value 614, after which it reduces sharply
Thus, under these circumstances it is advantageous to understand and design for, the thermal behavior of the cooling device under non-uniform chip heat load. To enable this understanding and design, it is desirable to characterize and measure the performance of these cooling devices when they are subjected to this spatially non-uniform chip power. Also, the chip power density is dependent on the application, i.e. the nature of its activity. Thus, the same chip under different applications will possess a different power density. Therefore, it is also desirable to design for a flexible or dynamically changing power map.